1. Field of the Invention
The present invention relates to semiconductor memory devices and, particularly to a semiconductor memory device allowing a data signal to be rewritten thereinto.
2. Description of the Background Art
FIG. 10 is a circuit block diagram showing a principal portion of a conventional dynamic random access memory (hereinafter DRAM). Referring to FIG. 10, the DRAM includes a plurality of memory cells MC arranged in rows and columns, a word line WL provided correspondingly to each row, a pair of bit lines BL and /BL provided correspondingly to each column, and a pair of write data lines WDL and /WDL. The DRAM further includes a write column select gate 50, a sense amplifier 55 and an equalizer 60 that are provided correspondingly to each column.
Write column select gate 50 includes N-channel MOS transistors 51-54. N-channel MOS transistors 51 and 52 are connected in series between bit line BL and write data line WDL, and N-channel MOS transistors 53 and 54 are connected in series between bit line /BL and write data line /WDL. N-channel MOS transistors 51 and 53 have respective gates connected to a write column select line WCSL and N-channel MOS transistors 52 and 54 have respective gates receiving signal WDE. Signal WDE is set to L level (logical low level) for write masking and set to H level (logical high level) in normal operation. When signal WDE has H level and write column select line WCSL designated according to column address signal CA is set to H level which is the selection level, N-channel MOS transistors 51-54 of the corresponding column are turned on to couple paired bit lines BL and /BL and paired write data lines WDL and /WDL.
Sense amplifier 55 includes N-channel MOS transistors 56 and 57 and P-channel MOS transistors 58 and 59. N-channel MOS transistors 56 and 57 are connected respectively between bit lines BL and /BL and a node N51, and have respective gates connected respectively to bit lines /BL and BL. P-channel MOS transistors 58 and 59 are connected respectively between bit lines BL and/BL and a node N52, and have respective gates connected respectively to bit lines /BL and BL. Nodes N51 and N52 receive sense amplifier activation signals SNL and SPL respectively. In a standby state, sense amplifier activation signals SNL and SPL are each set to potential VCC/2, i.e., a half of a power supply potential VCC. In an active state, sense amplifier activation signals SNL and SPL are set respectively to L and H levels. Sense amplifier activation signals SNL and SPL are set to L and H levels respectively to activate sense amplifier 55 which in turn amplifies a minute or considerably small potential difference between corresponding paired bit lines BL and /BL up to power supply potential VCC.
Equalizer 60 is activated when bit line equalize signal BLEQ is set to the activation level, L level, and accordingly precharges corresponding paired bit lines BL and /BL to bit line precharge potential VBL (=VCC/2).
FIG. 11 is a timing chart illustrating a write operation of the DRAM shown in FIG. 10. In a standby state, word line WL is set to the non-selection level, L level, to inactivate memory cell MC. Write column select line WCSL is also set to the non-selection level, L level, to make write column select gate 50 nonconductive. Equalizer 60 is activated to precharge paired bit lines BL and /BL to precharge potential VCC/2. Sense amplifier activation signals SPL and SNL are set to the immediate level VCC/2 to inactivate sense amplifier 55. Here, signal WDE is set to H level.
First, active command ACT and row address signal RA are provided, equalizer 60 is inactivated, and word line WL of a row according to row address signal RA is raised to the selection level, H level. Word line WL is thus set to H level to activate each memory cell MC corresponding to that word line WL. Then, a minute potential difference of a polarity according to data stored in memory cell MC is generated between paired bit lines BL and /BL. Then, sense amplifier activation signals SPL and SNL are set to H and L levels respectively to activate sense amplifier 55. Accordingly, the potential difference between paired bit lines BL and /BL is amplified to power supply potential VCC.
Second, write command WRT and column address signal CA are provided. Write column select line WCSL of a column according to column address signal CA is raised to the selection level, H level, to make write column select gate 50 of that column conductive. Accordingly, paired bit lines BL and /BL of that column and paired write data lines WDL and /WDL are coupled. In advance, write data lines WDL and /WDL are set respectively at L and H levels for example according to a write data signal. Then, the levels of respective bit lines BL and /BL of the selected column are converted to the levels of respective write data lines WDL and /WDL. The levels of bit lines BL and /BL of any non-selected column are maintained. After a predetermined time has passed, write column select line WCSL is lowered to the non-selection level, L level.
Third, precharge command PRE is provided. Word line WL is lowered to the non-selection level, L level, to inactivate memory cell MC. Sense amplifier activation signals SPL and SNL are set to the intermediate level, VCC/2, to inactivate sense amplifier 55. Equalizer 60 is activated and paired bit lines BL and /BL are set to bit line precharge potential VBL. In this way, the data signal is written.
FIG. 12 is a circuit block diagram showing a principal portion of another conventional DRAM. Referring to FIG. 12, this DRAM differs from the DRAM in FIG. 10 in that the former includes a write column select gate 61 instead of write column select gate 50. Write column select gate 61 includes N-channel MOS transistors 62-65. N-channel MOS transistors 62 and 63 are connected in series between bit line BL and a line of a ground potential GND. N-channel MOS transistors 64 and 65 are connected in series between bit line /BL and the line of ground potential GND. N-channel MOS transistors 62 and 64 have respective gates both connected to write column select line WCSL, and N-channel MOS transistors 63 and 65 have respective gates connected respectively to write data lines /WDL and WDL.
When write column select line WCSL is raised to the selection level, H level, N-channel MOS transistors 62 and 64 are turned on. When write data lines WDL and /WDL have H and L levels respectively, N-channel MOS transistor 65 is turned on while N-channel MOS transistor 63 is turned off. Then, bit line /BL is lowered to L level, and sense amplifier 55 raises bit line BL to H level. When write data lines WDL and /WDL have L and H levels respectively, N-channel MOS transistor 63 is turned on while N-channel MOS transistor 65 is turned off. Then, bit line BL is lowered to L level and sense amplifier 55 raises bit line /BL to H level. Except for the above-described details, the DRAM shown in FIG. 12 has the same structure and operation as those of the DRAM shown in FIG. 10 and description thereof is not repeated here.
High-speed writing into conventional DRAMs is possible in a page mode, in which column selection is performed multiple times successively for one activated memory-cell row, since it is merely necessary that write command WRT is input multiple times after active command ACT is applied once. However, in a random access mode in which row address signal RA and column address signal CA are changed each time write operation is carried out, the three steps shown in FIG. 11 are required for each write operation, which makes it difficult to speed up the write operation.
Specifically, random access of at least 50 MHz is possible to a static random access memory (hereinafter SRAM) while random access of as low as approximately 22 MHz is merely possible to a DRAM. This results in an obstacle for the DRAM to achieve functions of the SRAM implemented in a system LSI.
One object of the present invention is thus to provide a semiconductor memory device to which enhanced-speed random access is possible.
A semiconductor memory device according to the present invention includes: a memory block including a plurality of memory cells, a plurality of word lines, and a plurality of pairs of bit lines; a sense amplifier provided correspondingly to each pair of bit lines and activated in response to application of a first drive potential to a first node to amplify a potential difference generated between the bit lines of the corresponding bit line pair; a row decoder selecting one of the word lines according to a row address signal to activate each memory cell corresponding to the selected word line; a column decoder selecting one of the pairs of bit lines according to a column address signal; a pair of write data lines provided commonly to the pairs of bit lines; a write circuit, according to a write data signal, setting one of first and second write data lines included in the pair of write data lines to a first potential and setting the other of the first and second write data lines to a second potential; and a write column select gate transmitting, in write operation, the data signal on the pair of write data lines to the pair of bit lines selected by the column decoder. The write column select gate includes first and second transistors provided correspondingly to each pair of bit lines, having respective gate electrodes connected to the first and second write data lines respectively and having respective first electrodes both connected to the first node, and third and fourth transistors provided correspondingly to each pair of bit lines, having respective first electrodes connected to respective second electrodes of the first and second transistors and having respective second electrodes connected respectively to first and second bit lines of the corresponding pair of bit lines, the third and fourth transistors being rendered conductive, in the write operation, in response to selection of the corresponding pair of bit lines by the column decoder. Thus, even if the column decoder and the write circuit are activated prior to activation of the sense amplifier, the sense amplifier never operates unless a drive potential is applied to a predetermined node. The column decoder and the write circuit are then activated prior to activation of the sense amplifier so as to allow a data signal to be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which enhances the random access rate.
Preferably, the first and second transistors are provided commonly to the pairs of bit lines. The required number of the first and second transistors is thus reduced and the load capacitance of the write circuit accordingly decreases, which provides speedup of write operation.
Still preferably, the semiconductor memory device further includes a write control circuit activating, in response to a write command signal, the row decoder, the column decoder and the write circuit and thereafter applying the first drive potential to the first node to activate the sense amplifier. The write command can thus be issued simply since only one write command signal may be provided.
Still preferably, the semiconductor memory device further includes a precharge circuit provided correspondingly to each pair of bit lines for precharging the corresponding pair of bit lines to a predetermined potential. The write control circuit inactivates, after the write operation is completed, the row decoder, the column decoder, the write circuit and the sense amplifier, and activates the precharge circuit. Only one write command signal is necessary for the process up to precharging and thus the operation of issuing write command is further simplified.
Still preferably, the sense amplifier includes fifth and sixth transistors of N-channel type, connected respectively between the first and second bit lines and the first node, and having respective gate electrodes connected respectively to the second and first bit lines, and seventh and eighth transistors of P-channel type connected respectively between the first and second bit lines and a second node and having respective gate electrodes connected respectively to the second and first bit lines. The sense amplifier is activated in response to application of the first drive potential to the first node and application of the second drive potential to the second node. Then, the sense amplifier can readily be formed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.